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HANBit
HMS1M32M8LA
SRAM MODULE 4Mbyte(1Mx32Bit) ,LOW POWER,72Pin SIMM,5V Part No. HMS1M32M8LA
GENERAL DESCRIPTION
The HMS1M32M8LA is a static random access memory (SRAM) module containing 1,048,576 bits organized in a x32-bit configuration. The module consists of eight 512K x 8 SRAMs mounted on a 72-pin, double-sided, FR4-printed circuit board. The HMS1M32M8LA also support low data retention voltage for battery back-up operations with low data retention current. Eight chip enable inputs, (/CE0, /CE1, /CE2, /CE3, /CE4, /CE5, /CE6, /CE7) are used to enable the module's 4M bytes independently. Output enable(/OE) and write enable(/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible. Reading is
FEATURES
w Part identification - HMS1M32M8LA : SIMM design w Access times : 55ns, 70ns w High-density 4MByte design w High-reliability, low-power design w Single + 5V 0.5V power supply w Low data retention voltage : 2V(min) w Three state output and TTL-compatible w FR4-PCB design w Low profile 72-Pin SIMM PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PIN ASSIGNMENT
SYMBOL Vcc Vcc Vss Vss Vss Vss Vss DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 Vcc A0 A7 A1 A8 A2 A9 DQ12 DQ4 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ13 DQ5 DQ14 DQ6 DQ15 DQ7 /OE /CE3 A15 A14 /CE6 /CE7 /CE4 /CE5 A17 A16 /CE2 Vss DQ24 DQ16 DQ25 DQ17 DQ26 DQ18 PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ27 DQ19 A3 A10 A4 A11 A5 A12 Vcc A13 A6 DQ20 DQ28 DQ21 DQ29 DQ22 DQ30 DQ23 DQ31 Vss A18 /WE /CE1 /CE0
OPTIONS
w Timing 55ns access 70ns access w Packages 72-pin SIMM 72-pin ZIP
MARKING
-55 -70
M Z
SIMM TOP VIEW
URL: www.hbe.co.kr Rev. 1.0 (September / 2002)
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FUNCTIONAL BLOCK DIAGRAM
DQ 0-DQ31 A0-A18 32 19
HMS1M32M8LA
A0-18 /WE /OE /CE /CE7 A0-18 /WE /OE /CE /CE6 A0-18 /WE /OE /CE5 /CE DQ 8-15 /CE2 DQ16-23 /CE3 DQ24-31
A0-18 /WE /OE /CE DQ24-31
U4
U8
A0-18 /WE /OE /CE DQ16-23
U3
U7
A0-18 /WE /OE /CE /CE1 DQ 8-15
U2
U6
A0-18 /WE /OE /OE DQ 0-7 /WE /OE
A0-18 /WE /OE /CE /CE0 DQ 0-7
U1
/CE
U5
/CE4
URL: www.hbe.co.kr Rev. 1.0 (September / 2002)
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TRUTH TABLE
MODE STANDBY NOT SELECTED READ WRITE or ERASE NOTE: X means don't care /OE X H L X /CE H L L L /WE X H H L DQ HIGH-Z HIGH-Z Q D
HMS1M32M8LA
POWER STANDBY ACTIVE ACTIVE ACTIVE
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature Operating Temperature SYMBOL VIN,OUT VCC PD TSTG TA RATING -0.5V to +7.0V -0.5V to +7.0V 8W oC to +150oC -65 0oC to +70oC
w Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS ( TA=0 to 70 o C )
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.5* TYP. 5.0V 0 MAX 5.5V 0 Vcc+0.5V** 0.8V
VIL(Min.) = -2.0V (Pulse Width 10ns) for I 20 mA
** VIH(Min.) = Vcc+2.0V (Pulse Width 10ns) for I 20 mA
DC AND OPERATING CHARACTERISTICS (1) (0oC TA 70 oC ; Vcc = 5V 0.5V )
PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=5.0V, Temp=25 oC
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TEST CONDITIONS VIN = Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0mA IOL = 8.0mA
SYMBOL ILI IL0 VOH VOL
MIN -8 -8 2.4
MAX 8 8
UNITS A A V
0.4
V
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DC AND OPERATING CHARACTERISTICS (2)
DESCRIPTION Power Supply Current:Operating Power Supply Current:Standby TEST CONDITIONS IIO=0mA,/CE=VIL, VIN=VIL or VIH, Read /CE=VIH, Other inputs=VIL or VIH /CEVcc-0.2V, Other inputs=0~Vcc SYMBOL
HMS1M32M8LA
MAX -55 80 24 640 -70 80 24 640
UNIT
lCC lSB lSB1
mA mA A
CAPACITANCE
DESCRIPTION Input /Output Capacitance Input Capacitance TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN MAX 64 80 UNIT pF pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC TA 70 oC ; Vcc = 5V 0.5V, unless otherwise specified) Test conditions
PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load * See test condition of DC and Operating characteristics Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ VALUE 0.8 to 2.4V 5ns 1.5V CL=100pF + 1TTL
Output Load (A)
VL=1.5V
+3.3V
50 DOUT Z0=50 30pF DOUT 353
319 5pF*
URL: www.hbe.co.kr Rev. 1.0 (September / 2002)
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READ CYCLE
-55 PARAMETER Read Cycle Time Address Access Time Chip Select to Output Output Enable to Output Output Enable to Low-Z Output Chip Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change SYMBOL MIN tRC tAA tCO tOE tOLZ tLZ tOHZ tHZ tOH 5 10 0 0 10 20 20 55 55 55 25 5 10 0 0 10 MAX MIN 70
HMS1M32M8LA
-70 UNIT MAX ns 70 70 35 ns ns ns ns ns 25 25 ns ns ns
WRITE CYCLE
PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z SYMBOL tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW -55 MIN 55 45 0 45 40 0 0 25 0 5 20 MAX MIN 70 60 0 60 50 0 0 30 0 5 25 -70 MAX UNIT ns ns ns ns ns ns ns ns ns ns
TIMING DIAGRAMS
Please refer to timing diagram chart(II)
URL: www.hbe.co.kr Rev. 1.0 (September / 2002)
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FUNCTIONAL DESCRIPTION
/CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN
HMS1M32M8LA
SUPPLY CURRENT l SB, l SB1 lCC lCC lCC
Note: X means Don't Care
DATA RETENTION CHARACTERISTICS* (TA = 0 to 70 )
PARAMETER VCC for Data Retention Data Retention Current Data Retention Set-up Time Recovery Time * L-Version Only SYMBOL VDR IDR tSDR tRDR TEST CONDITION /CE VCC-0.2V VCC=3.0V, /CE VCC-0.2V VIN VCC-0.2V or VIN 0.2V See Data Retention Wave forms(below) 0 5 ns ns MIN 2 MAX 5.5 320 UNIT V A
DATA RETENTION WAVEFORM 1 (/CE Controlled)
tSDR Vcc 4.5V Data Retention Mode tRDR
2.2V VDR
/CE Vss
/CE Vcc- 0.2V
URL: www.hbe.co.kr Rev. 1.0 (September / 2002)
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PACKAGING DIMENSIONS
SIMM Design
HMS1M32M8LA
2.54 mm MIN 0.25 mm MAX Gold : 1.040.10 mm Solder : 0.9140.10 mm 1.270.08 mm
1.27
(Solder & Gold Plating Lead)
ORDERING INFORMATION
Part Number Density Org. Package Component Number 8EA 8EA Vcc SPEED
HMS1M32M8LA-55 HMS1M32M8LA-70
4MByte 4MByte
1Mx32bit 1Mx32bit
72Pin-SIMM 72Pin--SIMM
5.0V 5.0V
55ns 70ns
URL: www.hbe.co.kr Rev. 1.0 (September / 2002)
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